The present invention relates to digital signal processing systems, and more particularly to a method and apparatus for state-driven over-sampling in a Manchester decoder.
The Manchester protocol is a well-known encoding/decoding protocol for digital signals. It is often utilized in communication systems where a minimum transition density is required, or where a DC-balanced signal is required, for example, in AC-coupled communication links. The digital signal is encoded according to the Manchester protocol and decoded using a Manchester decoder.
The Manchester encoded signal comprises a self-clocking code with a minimum of one and a maximum of two level transitions per bit. A zero (i.e. logic LOW) is encoded as a Low-to-High transition, and a one (i.e. logic HIGH) is encoded as a High-to-Low transition. Between two identical bits of data in an encoded signal, there is an extra level transition which must be ignored by the decoder. As a result, the decoder needs some information about the bit timing. Conventional decoders typically utilize a clock with timing (i.e. frequency) that is a known multiple of the encoding clock for the Manchester signal.
To decode the received (i.e. encoded) digital signal, known Manchester decoder designs utilize two general approaches. One approach involves asynchronously over-sampling the encoded signal at a rate greater than 5 times the frequency of the signal. The other approach involves recovering a synchronous clock signal from the encoded digital signal and using the recovered clock to decode (i.e. read) the data in the received signal. To accurately recover the synchronous clock signal, a Phase Locked Loop or PLL clock recovery system is typically used in the decoder design, which as will be appreciated adds to the cost of the decoder.
It will be appreciated that both approaches, i.e. high over-sampling ratios or synchronous clock recovery, increase the complexity and cost of the Manchester decoder design. In addition, the frequencies involved with high over-sampling ratios tend to limit the design options for silicon implementations. For example, conventional Field Programmable Gate Array (FPGA) devices may not be suitable for such applications.
Accordingly, there remains a need for a decoder design suitable for Manchester encoded signals which overcomes the shortcomings of existing designs.
The present invention provides a method and apparatus for a Manchester decoder. According to one aspect of the invention, a low over-sampling ratio is utilized which makes the decoder suitable for implementation in a semi-custom silicon device, such as Field Programmable Gate Array (FPGA). The Manchester decoder design according to the present invention does not require generating a synchronous decoder clock, i.e. a clock which is synchronous with the received data signal. Accordingly, the need for a Phase Locked Loop (PLL) device is also eliminated.
In a first aspect, the present invention provides a decoder for decoding a signal encoded according to a Manchester protocol, the decoder comprises: (a) a sampling clock, and the sampling clock operates asynchronously with the encoded signal; (b) a sampling stage having an input port for receiving the encoded signal, and the sampling stage samples the encoded signal on a periodic basis in response to clock pulses from the sampling clock, and the sampling stage generates a stream of output pulses corresponding to logic states in the encoded signal; (c) a decoder stage having an input for receiving the stream of output pulses and includes a logic state machine, the logic state machine takes a group of sequential samples from the output pulse stream and determines an output logic state for the encoded signal, the output logic state is based on the sequence of logic levels in the group of sequential samples.
In another aspect, the present invention provides a method for decoding a signal encoded according to a Manchester protocol and having a known data rate, the method comprises the steps of: (a) sampling the encoded signal to generate a stream of pulse samples having logic levels based on logic states in the encoded signal, and the sampling is performed on the basis of a sample clocking signal, and the sample clocking signal runs asynchronously to the encoded signal; (b) taking a group of sequential pulse samples; (c) determining an output logic state for the encoded signal based on the logic levels of the sequential pulse samples in the group.
In a further aspect, the present invention provides a decoder implemented as an integrated circuit for decoding a signal encoded according to a Manchester protocol and having a known data rate, the decoder comprises: (a) a sampling clock which operates asynchronously with the encoded signal; (b) a sampling stage having an input port for receiving the encoded signal, and the input sampling stage samples the encoded signal on a periodic basis in response to clock pulses from the sampling clock, and the input sampling stage generates a stream of pulse samples corresponding to logic states in the encoded signal: (c) a decoder stage having an input for receiving the stream of pulse samples and including a logic state machine, the logic state machine takes a group of sequential pulse samples and determines an output logic state for the encoded signal, and the output logic state is based on the sequence of logic levels in the group of pulse samples.